With the rapid development of semiconductor manufacturing technology, the semiconductor device has been developed toward higher component density and higher integration degree. To reduce the size of the semiconductor device and to improve the integration degree of the semiconductor device, a multiple patterning process, e.g., a double patterning process, a triple patterning process, and a quadruple patterning process, has been developed.
The double patterning process can effectively reduce the difficulty of fabricating a small-sized pattern and has important applications in forming the small-sized pattern. The double patterning process includes a self-aligned double patterning (SADP) technique, a litho-etch-litho-etch-litho-etch (LELELE) technique, and a single-etch double patterning technique.
However, the semiconductor structure formed by the double patterning process has poor performance or has many restrictions on the design. For example, in the litho-etch-litho-etch-litho-etch (LELELE) technique, the alignment of multiple patterns is very difficult to control. In the self-aligned double patterning (SADP) technique, a spacing between two patterns or a pattern itself is determined by a thickness of a spacer wall. With single pattern linewidth or single spacing, the scope of the applications of the self-aligned double patterning (SADP) technique is limited. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.